A semiconductor device employable as a capacitor and a semiconductor memory cell employing the one transistor and one capacitor structure are available in the prior art. The semiconductor device employable as a capacitor available in the prior art has a structure consisting of a conductive layer horizontally produced on an insulator layer horizontally produced on a conductive region produced by introducing an impurity along the horizontal top surface of a semiconductor substrate. In other words, the semiconductor device employable as a capacitor available in the prior art has one dielectric plate arranged between two electrodes, all of them extending in the horizontal direction. Incidentally, the semiconductor memory cell of the one transistor and one capacitor structure available in the prior art has a field effect transistor of which the gate acts as a word line, of which the source is connected with a bit line and of which the drain is connected with a capacitor which is produced on top of the foregoing field effect transistor and which has one dielectric plate arranged between two electrodes, all of them extending in the horizontal direction. The other terminal of the capacitor is generally grounded.
Referring to drawings, the structure of a semiconductor memory cell of the one transistor and one capacitor structure available in the prior art and a process for producing same will be described below.
FIG. 1 is a plan view of plural semiconductor memory cells available in the prior art and FIG. 2 is a cross section of a semiconductor memory cell or of a portion thereof limited by the a-a' arrows shown in FIG. 1.
Referring to FIGS. 1 and 2, a part of the surface of a p-Si substrate 1500 is surrounded by an element separation area 1501 to define an active area 1502, in which a drain 1503, a gate 1507, a source 1504 and a drain 1503 are arranged in a row. In other words, one active area 1502 contains two field effect transistors which hold one source in common. The gate electrode 1507 which is made of a conductive poly crystalline Si layer on a gate insulator layer 1506 and of which the both sides are insulated by insulator side walls 1508, extends in the direction perpendicular to the page of the drawing to constitute a word line. The source 1504 is connected to a bit line 1510 which extends along the page from side to side or in the direction perpendicular to the word line 1507. The source 1504 is connected with the bit line 1510 via a bit contact 1511 which is produced aside of the source 1504 under the bit line 1510. The numeral 1509 indicates an insulator layer covering the field effect transistor described above. The bit line 1510 is produced on the insulator layer 1509, and the numeral 1512 indicates an insulator layer covering the bit line 1510. At a location corresponding to the drain 1503, a contact hole 1513 is produced in the insulator layers 1512 and 1509, to be buried by a conductive poly crystalline Si layer 1514 which extends on the surface of the insulator layer 1512. The contact between the drain 1503 and the conductive poly crystalline Si layer 1514 is called a cell contact 1515. The conductive poly crystalline Si layer 1514 is patterned to produce one electrode 1516 of a capacitor 1519. A dielectric layer 1517 is produced to cover the one electrode 1516. A conductive poly crystalline Si layer is produced on the dielectric layer 1517 to act as the other electrode 1518 of the capacitor 1519. The other electrode 1518 of the capacitor 1519 is connected with a low and fixed electric potential e.g. the ground level.
Referring to FIGS. 3 through 7, a process for producing the foregoing semiconductor memory cell will be described below.
Referring to FIG. 3, a LOCOS process or the like is employed to produce an element separation area 1501 on a semiconductor (Si in this example) substrate 1500 having one conductivity (p-type in this example).
Referring to FIG. 4, the top surface of the Si substrate 1500 is oxidized to produce a silicon dioxide layer 1506 which is scheduled to be a gate insulator layer, and a CVD process is employed to produce a conductive poly crystalline Si layer 1507. The conductive poly crystalline Si layer 1507 is patterned into the horizontal shape of a gate electrode 1507. The gate electrode 1507 is scheduled to be a word line (See FIG. 1). A CVD process is employed to produce a silicon dioxide layer 1508. The silicon dioxide layer 1508 is etch backed to be remained exclusively on the sides of the gate electrode 1507. Employing the gate electrode 1507 as a mask, an ion implantation process is conducted to introduce an impurity of the other conductivity (n-impurity in this case e.g. phosphorus, arsenic or antimony) in the top surface region of the Si substrate 1500 to produce a drain 1503 and a source 1504. At the edges of the drain 1503 and the source 1504, the impurity of the other conductivity diffuses toward beneath the gate insulator layer 1506 to a marginal extent, during the thermal processes conducted later, so that the drain 1503 and the source 1504 are allowed to contact with a channel which will occur during the operation of the field effect transistor. The drain 1503 is scheduled to be connected with a capacitor which is scheduled to be produced later and the source 1504 is scheduled to be connected with a bit line which extends in a direction perpendicular to the word line 1507 (See FIG. 2), via a bit contact 1511 (See FIG. 1) which is produced in the insulator layers 1509 and 1512 (See FIG. 2) produced on the Si substrate aside of the source 1504 (See FIG. 1).
Referring to FIG. 5, a CVD process is employed to produce a BPSG (silicate glass containing phosphorus and boron) layer 1509. After the bit contact 1511 and the bit line 1510 (See FIG. 1) referred to above are produced by employing CVD processes and photolithography processes, a CVD process is employed to produce a BPSG layer 1512 to insulate the bit line 1510 (See FIG. 1). A dry etching process is employed to produce a contact hole 1513 which reaches the drain 1503, penetrating the insulator layer 1509 and 1512.
Referring to FIG. 6, a CVD process is employed to deposit conductive Si in the contact hole 1513 and on the insulator layer 1512 to produce a conductive poly crystalline Si layer 1516, which is patterned to the horizontal shape of one electrode (or the first electrode) of a capacitor 1519 (See FIG. 7) covering the areas corresponding to the gate 1507 and a part of the neighboring gate 1507 of a field effect transistor belonging to the neighboring memory cell, as shown in the drawing.
Referring to FIG. 7, CVD processes are employed to produce a silicon nitride layer 1517 and a conductive poly crystalline Si layer 1518. Piled layers of the conductive poly crystalline Si layer 1516, the silicon nitride layer 1517 and the conductive poly crystalline Si layer 1518 constitute a capacitor 1519.
In this manner, produced is the capacitor 1519 which horizontally extends along the top surface of a filed effect transistor which acts as the transfer gate for a semiconductor memory cell. Accordingly, the capacity of a capacitor employed in a semiconductor memory cell having the one transistor and one capacitor structure available in the prior art, is determined by the horizontal area of a semiconductor memory cell or the horizontal dimension of a field effect transistor acting as the transfer gate for the semiconductor memory cell. Therefore, the amount of the capacity of the capacitor having the foregoing structure is inclined to be increasingly decreased in the wake of improvement in integration of semiconductor devices.
This drawback can be removed by an increase in the thickness of the conductive poly crystalline Si layer 1516, because this increase in the thickness of the conductive poly crystalline Si layer 1516 causes an increase in the vertical area of the side wall of the conductive poly crystalline Si layer 1516 (See FIG. 7) and results in an increase in the magnitude of the area with which the two electrodes of the capacitor 1519 faces to each other. However, this inevitably increases the thickness of the core domain of the semiconductor memory cells, causing to produce a step in the thickness between the core domain of the semiconductor memory cell and the domain of the peripheral circuits of the semiconductor memory cell. This step in the thickness between the core domain of the semiconductor memory cell and the domain of the peripheral circuits of the semiconductor memory cell causes various difficulties for producing interconnections between the memory cell proper and the peripheral circuits. The difficulties include difficulty which occurs during the exposure process in which the core domain of the semiconductor memory cell and the domain of the peripheral circuits are concurrently exposed in one step. In other words, if the step is larger than the depth of a focus of the optical equipment employed for the exposing process, it is difficult to equally focus on the independent two domains. Since the amount of the depth of a focus determines the amount of numerical aperture which determines the resolving power which limits the magnitude of minute processing, the foregoing drawback is more serious for production of a highly integrated semiconductor memory.
The foregoing step in the thickness between the core domain of the semiconductor memory cell and the domain of the peripheral circuits causes the other problem for spin coating a photoresist on the core domain of the semiconductor memory cell and the domain of the peripheral circuits. When a photoresist is spin coated, the top surface of the photoresist layer produced on the core domain of the semiconductor memory cell is flush with the photoresist layer produced on the domain of the peripheral circuits. This means that the thickness of the photoresist layer produced on the core domain of the semiconductor memory cell is thinner than that of the photoresist layer produced on the domain of the peripheral circuits. This causes possibility that the photoresist layer produced on the core domain of the semiconductor memory cell does not sufficiently function as an etching mask, due to its less thickness.